1. Field of the Invention
The present invention relates to a circuit and a method for generating an output signal having a variable pulse duty factor. Moreover, the present invention relates to a digital switching controller, and a motor vehicle which includes this type of circuit and this type of digital switching controller.
2. Description of the Related Art
Signals, for example clock signals or pulse width-modulated (PWM) signals, have a pulse duty factor, also referred to as the duty factor. The pulse duty factor defines the ratio of the pulse duration, i.e., the active signal component, to the period of the signal.
Clock signals having a pulse duty factor of 50%, or clock signals which may be generated, for example, from a basic clock pulse by bistable trigger elements or flip-flops, are easily implemented in digital technology. Thus, for example, a clock signal having one-half the frequency and a pulse duty factor of 25% or 75% may be derived from a basic clock pulse. The closer the pulse duty factor is to the 0% or 100% limit, the higher the basic clock pulse must be. In addition, only discrete values are settable for the pulse duty factor.
However, a clock pulse is often needed whose pulse duty factor may assume an arbitrary value. This is complicated by the fact that a correspondingly high basic clock pulse is quite often not available.
An important application for these types of clock pulses or clock signals is a digital switching controller, in which the main difficulty at the present time lies in converting the pulse duty factor computed from the digital component into an analog signal for controlling an output stage of the switching controller. For this purpose, it is common to either use a basic clock pulse which is much faster for the digital component, or to shift functions which may be solved digitally into the analog component.
A faster basic clock pulse imposes high requirements on the digital component. If, for example, a switching controller frequency of 1 MHz with a pulse duty factor which is precisely settable to approximately 1% is to be implemented, this would require a digital clock pulse of 1 MHz×27=128 MHz, which at the present time is hardly achievable in the automotive field, for example.
A shift into the analog component results in a high level of complexity for the signal conversion, for example in the form of a fast D/A converter, a comparator, and a saw-tooth voltage generator having a precise amplitude.